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| rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adv7196a one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 multiformat progressive scan/hdtv encoder with three 11-bit dacs, 10-bit data input, and macrovision functional block diagram cgms macrovision sharpness filter control and adaptive filter control test pattern generator and delay and gamma correction y0 y9 cr0?r9 cb0?b9 chroma 4:2:2 to 4:4:4 (ssaf) 2 inter- polation timing generator sync generator i 2 c mpu port clkin horizontal sync vertical sync blanking reset adv7196a dac control block dac a (y) dac b dac c v ref reset comp 11-bit+ sync dac 11-bit dac 11-bit dac luma ssaf chroma 4:2:2 to 4:4:4 (ssaf) features input formats ycrcb in 2 10-bit (4:2:2) or 3 10-bit (4:4:4) format compliant to smpte-293m (525p), itu-r.bt1358 (625p), smpte274m (1080i), smpte296m (720p) and any other high definition standard using async timing mode rgb in 3 10 bit (4:4:4) format output formats yprpb progressive scan (eia-770.1, eia-770.2) yprpb hdtv (eia-770.3) rgb levels compliant to rs-170 and rs-343a 11-bit and sync (dac a) 11-bit dacs (dac b, dac c) programmable features internal test pattern generator with color control y/c delay ( ) gamma correction individual dac on/off control 54 mhz output (2 oversampling) sharpness filter with programmable gain/attenuation programmable adaptive filter control undershoot limiter i 2 c ? filter vbi open control macrovision rev. 1.0 (525p) cgms-a (525p) 2-wire serial mpu interface single supply 3.3 v operation 52-mqfp package applications progressive scan/hdtv display devices dvd players mpeg 2 at 81 mhz progressive scan/hdtv projection systems digital video systems high resolution color graphics image processing/instrumentation digital radio modulation/video signal reconstruction i 2 c is a registered trademark of philips corporation. general description the adv7196a is a triple high-speed, digital-to-analog encoder on a single monolithic chip. it consists of three high-speed video d/a converters with ttl-compatible inputs. the adv7196a has three separate 10-bit-wide input ports which accept data in 4:4:4 10-bit ycrcb or rgb or 4:2:2 10-bit ycrcb. this data is accepted in progressive scan format at 27 mhz or hdtv format at 74.25 mhz or 74.1758 mhz. for any other high-definition standard but smpte 293m, itu-r bt.1358, smpte274m or smpte296m the async timing mode can be used to input data to the adv7196a. for all standards, external horizontal, vertical, and blanking signals or eav/sav codes control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signals. the adv7196a outputs analog yprpb progressive scan format complying to eia-770.1, eia-770.2; yprpb hdtv complying to eia-770.3; rgb complying to rs-170/rs-343a. the adv7196a requires a single 3.3 v power supply, an optional external 1.235 v reference and a 27 mhz clock in progressive scan mode or a 74.25 mhz (or 74.1758 mhz) clock in hdtv mode. in progressive scan mode, a sharpness filter with programmable gain allows high-frequency enhancement on the luminance signal. programmable adaptive filter control, which may be used, allows removal of ringing on the incoming y data. the adv7196a supports cgms-a data control generation and the macrovision anticopy algorithm in 525p mode. the adv7196a is packaged in a 52-lead mqfp package.
rev. 0 adv7196a C2C table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . . 1 3.3 v specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 v dynamic?pecifications . . . . . . . . . . . . . . . . . . 4 3.3 v timing?pecifications . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . 8 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin function descriptions . . . . . . . . . . . . . . . . . . 9 functional description . . . . . . . . . . . . . . . . . . . . 10 digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 analog outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 i 2 c filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 undershoot limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 internal test pattern generator . . . . . . . . . . . . . . . . . . . . 10 y/crcb delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 gamma correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 54 mhz operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 programmable sharpness filter . . . . . . . . . . . 10 programmable adaptive filter control . . 10 input/output configuration . . . . . . . . . . . . . . . . . . . . . . . 11 mpu port description . . . . . . . . . . . . . . . . . . . . . . . 11 register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 register programming . . . . . . . . . . . . . . . . . . . . . 13 subaddress register (sr7?r0) . . . . . . . . . . . . . . . . . . . 13 register select (sr6?r0) . . . . . . . . . . . . . . . . . . . . . . . . 13 progressive scan mode . . . . . . . . . . . . . . . . . . . . . 14 mode register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 mr0 (mr07 mr00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 mr0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 14 output standard selection (mr00?r01) . . . . . . . . . . . 14 input control signals (mr02?r03) . . . . . . . . . . . . . . . 14 input standard (mr04) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 reserved (mr05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 dv polarity (mr06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 macrovision (mr07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 mode register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 mr1 (mr17 mr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 mr1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 16 pixel data enable (mr10) . . . . . . . . . . . . . . . . . . . . . . . . 16 input format (mr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 test pattern enable (mr12) . . . . . . . . . . . . . . . . . . . . . . 16 test pattern hatch/frame (mr13) . . . . . . . . . . . . . . . . . 16 vbi open (mr14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 undershoot limiter (mr15?r16) . . . . . . . . . . . . . . . . 16 sharpness filter (mr17) . . . . . . . . . . . . . . . . . . . . . . . . . 16 mode register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 mr1 (mr27 mr20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 mr2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 17 y delay (mr20?r22) . . . . . . . . . . . . . . . . . . . . . . . . . 17 color delay (mr23?r25) . . . . . . . . . . . . . . . . . . . . . . 17 cgms enable (mr26) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 cgms crc (mr27) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 mode register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mr3 (mr37 mr30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mr3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 18 hdtv enable (mr30) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 reserved (mr31?r32) . . . . . . . . . . . . . . . . . . . . . . . . . 18 dac a control (mr33) . . . . . . . . . . . . . . . . . . . . . . . . . 18 dac b control (mr34) . . . . . . . . . . . . . . . . . . . . . . . . . 18 dac c control (mr35) . . . . . . . . . . . . . . . . . . . . . . . . . 18 interpolation (mr36) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 reserved (mr37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mode register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mr4 (mr47 mr40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mr4 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 18 timing reset (mr40) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mode register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mr5 (mr57 mr50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mr5 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 18 reserved (mr50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 rgb mode (mr51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 sync on prpb (mr52) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 color output swap (mr53) . . . . . . . . . . . . . . . . . . . . . . 18 gamma curve (mr54) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 gamma correction (mr55) . . . . . . . . . . . . . . . . . . . . . . 19 adaptive mode control (mr56) . . . . . . . . . . . . . . . . . . . 19 adaptive filter control (mr57) . . . . . . . . . . . . . . . . . . . 19 color y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 cy (cy7 cy0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 color cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ccr (ccr7?cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 color cb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ccb (ccb7?cb0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 mode register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mr6 (mr67 mr60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mr6 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 20 mr67?r60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 cgms data registers 2? . . . . . . . . . . . . . . . . . . . . 20 cgms2 (cgms27?gms20) . . . . . . . . . . . . . . . . . . . . 20 cgms1 (cgms17?gms10) . . . . . . . . . . . . . . . . . . . . 20 cgms0 (cgms07?gms00) . . . . . . . . . . . . . . . . . . . . 20 filter gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 fg (fg7 fg0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 fg bit description . . . . . . . . . . . . . . . . . . . . . . . . . . 21 filter gain a (fg3?g0) . . . . . . . . . . . . . . . . . . . . . . . . 21 filter gain b (fg4?g7) . . . . . . . . . . . . . . . . . . . . . . . . 21 gamma correction registers 0?3 . . . . . . . . . . 21 (gamma correction 0?3) . . . . . . . . . . . . . . . . . . 21 sharpness filter control and adaptive filter control . . . . . . . . . . . . . . . . . 22 sharpness filter mode . . . . . . . . . . . . . . . . . . . . . 22 adaptive filter mode . . . . . . . . . . . . . . . . . . . . . . . 22 adaptive filter gain 1 . . . . . . . . . . . . . . . . . . . . . . 23 afg1 (afg1)7? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 adaptive filter gain 2 . . . . . . . . . . . . . . . . . . . . . . 23 afg2 (afg2)7? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 rev. 0 adv7196a C3C adaptive filter gain 3 . . . . . . . . . . . . . . . . . . . . . . 23 afg3 (afg3)7? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 adaptive filter threshold a . . . . . . . . . . . . . . . 23 afta (afta)7? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 adaptive filter threshold b . . . . . . . . . . . . . . . 23 aftb (aftb)7? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 adaptive filter threshold c . . . . . . . . . . . . . . . 23 aftc (aftc)7? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 sharpness filter and adaptive filter application examples . . . . . . . . . . . . . . . . . . . . . 24 sharpness filter application . . . . . . . . . . . . . . . . . . . . . . 24 adaptive filter control application . . . . . . . . . . . . . . . . . 25 hdtv mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 mode register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 mr0 (mr07 mr00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 hexmr0 bit description . . . . . . . . . . . . . . . . . . . . . 26 output standard selection (mr00?r01) . . . . . . . . . . . 26 input control signals (mr02?r03) . . . . . . . . . . . . . . . 26 reserved (mr04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 input standard (mr05) . . . . . . . . . . . . . . . . . . . . . . . . . . 26 dv polarity (mr06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 reserved (mr07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 mode register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 mr1 (mr17 mr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 mr1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 27 pixel data enable (mr10) . . . . . . . . . . . . . . . . . . . . . . . . 27 input format (mr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 test pattern enable (mr12) . . . . . . . . . . . . . . . . . . . . . . 27 test pattern hatch/frame (mr13) . . . . . . . . . . . . . . . . . 27 vbi open (mr14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 reserved (mr15?r17) . . . . . . . . . . . . . . . . . . . . . . . . . 27 mode register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mr1 (mr27 mr20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mr2 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 28 y delay (mr20?r22) . . . . . . . . . . . . . . . . . . . . . . . . . 28 color delay (mr23?r25) . . . . . . . . . . . . . . . . . . . . . . 28 reserved (mr26?r27) . . . . . . . . . . . . . . . . . . . . . . . . . 28 mode register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mr3 (mr37 mr30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mr3 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 28 hdtv enable (mr30) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 reserved (mr31?r32) . . . . . . . . . . . . . . . . . . . . . . . . . 28 dac a control (mr33) . . . . . . . . . . . . . . . . . . . . . . . . . 28 dac b control (mr34) . . . . . . . . . . . . . . . . . . . . . . . . . 28 dac c control (mr35) . . . . . . . . . . . . . . . . . . . . . . . . . 28 reserved (mr36?r37) . . . . . . . . . . . . . . . . . . . . . . . . . 28 mode register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mr4 (mr47 mr40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mr4 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 29 timing reset (mr40) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mode register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mr5 (mr57 mr50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mr5 bit description . . . . . . . . . . . . . . . . . . . . . . . . . 29 reserved (mr50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 rgb mode (mr51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 sync on prpb (mr52) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 color output swap (mr53) . . . . . . . . . . . . . . . . . . . . . . 29 reserved (mr54?r57) . . . . . . . . . . . . . . . . . . . . . . . . . 29 dac termination and layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 pc board layout considerations . . . . . . . . . . 30 supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 digital signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . 31 analog signal interconnect . . . . . . . . . . . . . . . . . . . . . . . 31 video output buffer and optional output filter . . . . . . . 31 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 36 rev. 0 C4C adv7196a?pecifications 3.3 v specifications parameter min typ max unit test conditions static performance resolution (each dac) 11 bits integral nonlinearity 1.5 lsb differential nonlinearity 0.9 2.0 lsb digital outputs output high voltage, v ol 0.4 v i sink = 3.2 ma output low voltage, v oh 2.4 v i source = 400 a three state leakage current 10 av in = 0.4 v three state output capacitance 4 pf digital and control inputs input high voltage, v ih 2v input low voltage, v il 0.8 0.65 v input current, i in 01 av in = 0.0 v or v dd input capacitance, c in 4pf analog outputs full-scale output current 3.92 4.25 4.56 ma dac a output current range 3.92 4.25 4.56 ma dac a full-scale output current 2.54 2.83 3.11 ma dac b, c output current range 2.39 2.66 2.93 ma dac b, c dac-to-dac matching 1.4 % output compliance range, v oc 0 1.4 v output impedance, r out 100 k ? output capacitance, c out 7pf voltage reference (external) reference range, v ref 1.112 1.235 1.359 v power requirements i dd 2 25 35 ma 1 interpolation i dd 2 51 60 ma 2 interpolation i dd 2 40 ma hdtv mode (with f clk = 74.25 mhz) i aa 3, 4 11 15 ma 1 interpolation, 2 interpola- tion, and hdtv mode i pll 6.0 12 ma 1 interpolation, 2 interpola- tion, and hdtv mode power supply rejection ratio 0.01 %/% notes 1 guaranteed by characterization. 2 i dd or the circuit current is the continuous current required to drive the digital core without i pll . 3 i aa is the total current required to supply all dacs including the v ref circuitry. 4 all dacs on. specifications subject to change without notice. (v aa = 3.15 v to 3.45 v, v ref = 1.235 v, r set = 2470 , r load = 300 . all specifications t min to t max (0 c to 70 c) unless otherwise noted.) 3 v dynamic?pecifications parameter min typ max unit luma bandwidth 13.5 mhz chroma bandwidth 6.75 mhz signal-to-noise ratio 64 db luma ramp unweighted chroma/luma delay inequality 0 ns specifications subject to change without notice. (v aa = 3.15 v to 3.45 v, v ref = 1.235 v, r set = 2470 , r load = 300 . all specifications t min to t max (0 c to 70 c) unless otherwise noted.) rev. 0 C5C adv7196a 3.3 v timing?pecifications p arameter min typ max unit conditions mpu port 1 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 s sclock low pulsewidth, t 2 1.3 s hold time (start condition), t 3 0.6 s after this period the 1st clock is generated setup time (start condition), t 4 0.6 s relevant for repeated start condition data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s reset low time 100 ns analog outputs analog output delay 2 10 ns analog output skew 0.5 ns clock control and pixel port 3 f clk 27 mhz progressive scan mode f clk 74.25 mhz hdtv mode f clk 81 mhz async timing mode and 1 interpolation clock high time t 9 5.0 1.5 ns clock low time t 10 5.0 2.0 ns data setup time t 11 2.0 ns data hold time t 12 4.5 ns control setup time t 11 7.0 ns control hold time t 12 4.0 ns pipeline delay 16 clock cycles for 4:4:4 pixel input format at 1 oversampling pipeline delay 29 clock cycles for 4:4:4 or 4:2:2 pixel input format at 2 oversampling notes 1 guaranteed by characterization. 2 output delay measured from 50% point of the rising edge of clock to the 50% point of dac output full-scale transition. 3 data: cb/cr [9?], cr [9?], y [9:0] control: hsync / sync , vsync /tsync, dv specifications subject to change without notice. (v aa = 3.15 v to 3.45 v, v ref = 1.235 v, r set = 2470 , r load = 300 . all specifications t min to t max (0 c to 70 c) unless otherwise noted.) rev. 0 adv7196a C6C b0 b1 b2 b3 bxxx bxxx clock pixel input data r0 g0 r1 g1 r2 g2 g3 rxxx gxxx rxxx gxxx t 11 t 12 t 9 t 10 t 9 clock high time t 10 clock low time t 11 data setup time t 12 data hold time figure 1. 4:4:4 rgb input data format timing diagram clock pixel input data y0 cb0 y1 cr0 y2 cb1 cr1 yxxx cbxxx yxxx crxxx t 11 t 12 t 9 t 10 t 9 clock high time t 10 clock low time t 11 data setup time t 12 data hold time figure 2. 4:2:2 input data format timing diagram cr0 cr1 cr2 cr3 crxxx clock pixel input data y0 cb0 y1 cb1 y2 cb2 cb3 yxxx cbxxx yxxx cbxxx t 11 t 12 t 9 t 10 crxxx t 9 clock high time t 10 clock low time t 11 data setup time t 12 data hold time figure 3. 4:4:4 ycrcb input data format timing diagram rev. 0 adv7196a C7C a min = 16 clkcycles (525p) a min = 12 clkcycles (625p) a min = 44 clkcycles (1080i) a min = 70 clkcycles (720p) pixel data dv vsync hsync yyyy cr cr cr cr cb cb cb cb b a b min = 122 clkcycles (525p) b min = 132 clkcycles (625p) b min = 236 clkcycles (1080i) b min = 300 clkcycles (720p) figure 4. input timing diagram t 3 t 2 t 6 t 1 t 7 t 3 t 4 t 8 sda scl t 5 figure 5. mpu port timing diagram rev. 0 adv7196a C8C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adv7196a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v voltage on any digital pin . . . . gnd ?0.5 v to v aa + 0.5 v ambient operating temperature (t a ) . . . . . 40 c to +85 c storage temperature (t s ) . . . . . . . . . . . . . . 65 c to +150 c infrared reflow soldering (20 secs) . . . . . . . . . . . . . . . 225 c vapor phase soldering (1 minute) . . . . . . . . . . . . . . . . 220 c i out to gnd 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to v aa pin configuration 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 13 12 pin 1 identifier top view (not to scale) 39 38 37 36 35 34 33 32 31 30 29 28 27 adv7196a cr[0] cr[1] cr[2] cr[3] cr[4] cr[5] cr[6] cr[7] cr[8] cr[9] v aa clkin agnd gnd cb/cr[0] cb/cr[1] cb/cr[2] cb/cr[3] cb/cr[4] cb/cr[5] cb/cr[6] cb/cr[7] cb/cr[8] cb/cr[9] alsb reset v dd y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] y[8] y[9] v dd gnd v ref r set comp dac b v aa dac a agnd dac c sda scl hsync / sync vsync /tsync dv ordering guide model temperature range package description package option adv7196aks 0 c to 70 c plastic quad flatpack (mqfp) s-52 notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. rev. 0 adv7196a C9C pin function descriptions pin mnemonic input/output function 1, 12 v dd p digital power supply 2?1 y0?9 i 10-bit progressive scan/hdtv input port for y data. input for g data when rgb data is input. 13, 52 gnd g digital ground 14?3 cr0?r9 i 1 0-bit progressive sc an/hdtv input port for color data in 4:4:4 input m ode. in 4:2:2 mode this input port is not used. input port for r data when rgb data is input. 24, 35 v aa p analog power supply 25 clkin i pixel clock input. requires a 27 mhz reference clock for standard operation in progressive scan mode or a 74.25 mhz (74.1758 mhz) reference clock in hdtv mode. 26, 33 agnd g analog ground 27 dv i video blanking control signal input 28 vsync/ i vsync , vertical sync control signal input or tsync input control signal in tsync async timing mode 29 hsync/ i hsync , horizontal sync control signal input or sync input control signal in sync async timing mode 30 scl i mpu port serial interface clock input 31 sda i/o mpu port serial data input/output 32 dac c o color component analog output of input data on cb/cr9? input pins 34 dac a o y analog output 36 dac b o color component analog output of input data on cr9?r0 input pins 37 comp o compensation pin for dacs. connect 0.1 f capacitor from comp pin to v aa . 38 r set i a 2470 ? resistor (for input ranges 64?40 and 64?60; output standards eia-770.1?ia-770.3) must be connected from this pin to ground and is used to control the amplitudes of the dac outputs. for input ranges 0?023 (output standards rs-170, rs-343a) the r set value must be 2820 ? . 39 v ref i/o optional external voltage reference input for dacs or voltage reference output (1.235 v) 40 reset i this input resets the on-chip timing generator and sets the adv7196a into default register setting. reset is an active low signal. 41 alsb i ttl address input. this signal sets up the lsb of the mpu address. when this pin is tied high, the i 2 c filter is activated which reduces noise on the i 2 c interface. when this pin is tied low, the input bandwidth on the i 2 c interface is increased. 42?1 cb/cr9? i 1 0-bit progressive scan/hdtv input port for c olor data. in 4:2:2 mode the multiplexed crcb data must be input on these pins. input port for b data when rgb is input. rev. 0 adv7196a C10C functional description digital inputs the digital inputs of the adv7196a are ttl compatible. 30-bit ycrcb or rgb pixel data in 4:4:4 format or 20-bit ycrcb pixel data in 4:2:2 format is latched into the device on the rising edge of each clock cycle at 74.25 mhz or 74.1758 in hdtv mode. it is also possible to input 3 10 bit rgb data in 4:4:4 to the adv7196a. it is recommended to input data in 4:2:2 mode to make use of the chroma ssafs on the adv7196a. as can be seen in the figure below, this filter has a 0 db pass band response and prevents signal com ponents being folded b ack in to the fre- quency band. in 4:4:4: input mode, the video data is already interpolated by the external input device and the chroma ssafs of the adv7196a are bypassed. rbw 10khz vbw 300hz swp 17.0sec start 100khz stop 20.00mhz rl 10.0dbm 10db/ 3.18mhz atten 10db vavg 1 mkr 0db figure 6. adv7196a ssaf response to a 2.5 mhz chroma sweep using 4:2:2 input mode rbw 10khz vbw 300hz swp 17.0sec start 100khz stop 20.00mhz rl 10.0dbm 10db/ 3.12mhz atten 10db vavg 4 mkr 3.00db figure 7. conventional filter response to a 2.5 mhz chroma sweep using 4:4:4 input mode control signals the adv7196a accepts sync control signals accompanied by valid 4:2:2 or 4:4:4 data. these external horizontal, vertical and blanking pulses (or eav/sav codes) control the insertion of appropriate sync information into the output signals. analog outputs the analog y signal is output on the 11-bit + sync dac a, the color component analog signals on the 11-bit dacs b, c conforming to eia-770.1 or eia-770.2 standards in ps mode or eia-770.3 in hdtv mode. r set has a value of 2470 ? (eia-770.1, eia-770.2, eia-770.3), r load has a value of 300 ? . for rgb outputs conforming to rs-170/rs-343a output standards r set must have a value of 2820 ? . i 2 c filters a selectable internal i 2 c filter allows significant noise reduction on the i 2 c interface. in setting alsb high, the input bandwidth on the i 2 c lines is reduced and pulses of less than 50 ns are not passed to the i 2 c controller. setting alsb low allows gre ater input bandwidth on the i 2 c lines. undershoot limiter a limiter can be applied to the y data before it is applied to the dacs. available limit values are ?.5 ire, ? ire, ?1 ire below blank- ing. this functionality is available in progressive scan mode only. internal test pattern generator the adv7196a can generate a cross-hatch pattern (white lines against a black background). additionally, the adv7196a can output a uniform color pattern. the color of the lines or uniform field/frame can be programmed by the user. y/crcb delay the y output and the color component outputs can be delayed wrt the falling edge of the horizontal sync signal by up to four clock cycles. gamma correction gamma correction may be performed on the luma data. the user has the choice to use either of two different gamma curves, a or b. at any one time one of these curves is operational if gamma correction is enabled. gamma correction allows the mapping of the luma data to a user-defined function. 54 mhz operation in progressive scan mode, it is possible to operate the three out- put dacs at 54 mhz or 27 mhz. the adv7196a is supplied with a 27 mhz clock synced with the incoming data. if requ ired, a second stage interpolation filter interpolates the data to 54 mhz before it is applied to the three output dacs. the second stage interpolation filter is controlled by mr36. after applying a reset it is recommended to toggle this bit. before toggling this bit, 3ehex must be written to address 09hex. programmable sharpness filter sharpness filter mode is applicable to the y data only in p rogres- sive scan mode. the desired frequency response can be chosen by the user in programming the correct value via the i 2 c. the variation of frequency responses can be seen in the figures on the following pages. programmable adaptive filter control if the adaptive filter mode is enabled (progressive scan mode only), it is possible to compensate for large edge transitions on the incoming y data. sensitivity and attenuation are all program- mable over the i 2 c. for further information refer to sharpness filter control and adaptive filter control section. rev. 0 adv7196a C11C input/output configuration table i shows possible input/output configurations when using the adv7196a. table i. input format output ycrcb progressive scan 4:2:2 2 4:4:4 1 or 2 ycrcb hdtv 4:2:2 1 4:4:4 1 rgb progressive scan 4:4:4 2 rgb hdtv 4:4:4 1 async timing mode all inputs 1 10 0 80 40 50 60 70 20 30 10 5 10152025 0 30 figure 8. 2 interpolation filter C y-channel 10 0 80 40 50 60 70 20 30 10 5 10152025 0 30 figure 9. interpolation filter C crcb channels for 4:2:2 input data 10 0 80 40 50 60 70 20 30 10 5 10152025 0 30 figure 10. interpolation filter C crcb channels for 4:4:4 input data mpu port description the adv7196a support a 2-wire serial (i 2 c-compatible) micro- processor bus driving multiple peripherals. two inputs, serial data (sda) and serial clock (scl), carry information between any device connected to the bus. each slave device is recognized by a unique address. the adv7196a has four possible slave ad dresses for both read and write operations. these are unique addresses for each device and illustrated in figure 11. the lsb sets either a read or write operation. logic level ? corresponds to a read operation while logic level ??corresponds to a write opera- tion. a1 is set by setting the alsb pin of the adv7196a to l ogic level ??or logic level ?.?when alsb is set to ?,?there is greater input bandwidth on the i 2 c lines, which allows high- speed data transfers on this bus. when alsb is set to ?,?there is reduced input bandwidth on the i 2 c lines, which means that pulses of less than 50 ns will not pass into the i 2 c internal control- ler. this m ode is recommended for noisy systems. 1 x 1 0 1 01 a1 address control set up by alsb read/ write control 0 write 1read figure 11. slave address to control the various devices on the bus the following protocol must be followed. first the master initiates a data transfer by establishing a start condition, defined by a high-to-low transi- tion on sda while scl remains high. this indicates that an address/data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w bit). the bits are transferred from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sda and scl lines waiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. rev. 0 adv7196a C12C a logic ??on the lsb of the first byte means that the master will write information to the peripheral. a logic ??on the lsb of the first byte means that the master will read information from the peripheral. the adv7196a acts as a standard slave device on the bus. the data on the sda pin is 8 bits long supporting the 7-bit addresses plus the r/ w bit. it interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses auto- increment allowing data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop con- dition. the user can also access any unique subaddress register on a one by one basis without having to update all the registers. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, then these cause an immedi- ate jump to the idle condition. during a given scl high period the user should only issue one start condition, one stop condition or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the adv7196a will not issue an acknowledge and will return to the idle condition. if in autoincrement mode, the user exceeds the highest subaddress then the following action will be taken: 1. in read mode, the highest subaddress register contents will continue to be output until the master device issues a no- acknowledge. this indicates the end of a read. a no-acknowledge condition is where the sda line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the adv7196a and the part will return to the idle condition. 1 78 9 1 789 1 78 9 p s start addr r/ w ack subaddress ack data ack stop sdata sclock figure 12. bus data transfer figure 12 illustrates an example of data transfer for a read sequence and the start and stop conditions. figure 13 shows bus write and read sequences. register accesses the mpu can write to or read from all of the registers of the adv7196a except the subaddress registers, which are write-only registers. the subaddress register determines which register the next read or write operation accesses. all communications with the part through the bus begin with an access to the subaddress register. a read/write operation is per- formed from/to the target address which then increments to the next address until a stop command on the bus is performed. data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data a (s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data a(m) a (m) data p write sequence read sequence s = start bit a(s) = acknowledge by slave a (s) = no-acknowledge by slave p = stop bit a(m) = acknowledge by master a (m) = no-acknowledge by master figure 13. write and read sequence rev. 0 adv7196a C13C register programming the following section describes the functionality of each register. all registers can be read from as well as written to unless other- wise stated. subaddress register (sr7?r0) the communications register is an eight bit write-only register. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. figure 14 shows the various operations under the control of the subaddress register. ??should always be written to sr7. register select (sr6?r0) these bits are set up to point to the required starting address. sr4 sr3 sr2 sr1 sr0 sr7 sr6 sr5 address sr6 sr5 sr4 sr3 sr2 sr1 sr0 00h 0000000 mode regi ster 0 01h 0000001 mode regi ster 1 02h 0000010 mode regi ster 2 03h 0000011 mode regi ster 3 04h 0000100 mode regi ster 4 05h 0000101 mode regi ster 5 06h 0000110 color y 07h 0000111 color cr 08h 0001000 color cb 09h 0001001 mode regi ster 6 0ah 0001010 r eserved 0bh 0001011 r eserved 0ch 0001100 r eserved 0eh 0001110 r eserved 0fh 0001111 r eserved 10h 0010000 filter gain 11h 0010001 cgms data regi ster 0 12h 0010010 cgms data regi ster 1 13h 0010011 cgms data regi ster 2 14h 0010100 gamma correction register 0 15h 0010101 gamma correction register 1 16h 0010110 gamma correction register 2 17h 0010111 gamma correction register 3 18h 0011000 gamma correction register 4 19h 0011001 gamma correction register 5 1ah 0011010 gamma correction register 6 1bh 0011011 gamma correction register 7 1ch 0011100 gamma correction register 8 1dh 0011101 gamma correction register 9 1eh 0011110 gamma correction register 10 1fh 0011111 gamma correction register 11 20h 0100000 gamma correction register 12 21h 0100001 gamma correction register 13 22h 0100010 adaptive filter gain 1 23h 0100011 adaptive filter gain 2 24h 0100100 adaptive filter gain 3 25h 0100101 adaptive filter threshold a 26h 0100110 adaptive filter threshold b 27h 0100111 adaptive filter threshold c adv7196a subaddress register zero should be written here sr7 figure 14. subaddress registers in progressive scan mode sr4 sr3 sr2 sr1 sr0 sr7 sr6 sr5 address sr6 sr5 sr4 sr3 sr2 sr1 sr0 00h 0000000 mode regi ster 0 01h 0000001 mode regi ster 1 02h 0000010 mode regi ster 2 03h 0000011 mode regi ster 3 04h 0000100 mode regi ster 4 05h 0000101 mode regi ster 5 06h 0000110 color y 07h 0000111 color cr 08h 0001000 color cb adv7196a subaddress register zero should be written here sr7 figure 15. subaddress registers in hdtv mode rev. 0 adv7196a C14C progressive scan mode mode register 0 mr0 (mr07?r00) (address (sr4?r0) = 00h) figure 16 shows the various operations under the control of mode register 0. mr0 bit description output standard selection (mr00?r01) these bits are used to select the output levels for the adv7196a. if eia-770.2 (mr01?0 = ?0? is selected the output levels will be: 0 mv for blanking level, 700 mv for peak white for the y chan nel, 350 mv for pr, pb outputs and ?00 mv for sync. sync insertion on the pr, pb channels is optional. if eia-770.1 (mr01?0 = ?1? is selected the output levels will be: 0 mv for blanking level, 714 mv for peak white for the y chan- nel, 350 mv for pr, pb outputs and ?86 mv for sync. o ptional sync insertion on the pr, pb channels is not possible. if full i/p range (mr01?0 = ?0? is selected the output levels will be 0 mv for blanking level, 700 mv for peak white for the y channel, 350 mv for pr, pb outputs and ?00 mv for sync. sync insertion on the pr, pb channels is optional. this mode is used for rs-170, rs-343a standard output compatibility. refer to appendix for output level plots. input control signals (mr02?r03) these control bits are used to select whether data is input with external horizontal, vertical and blanking sync signals or if the data is input with embedded eav/sav codes. an asynchronous timing mode is also available using tsync, sync and dv as input control signals. these control signals have to be programmed by the user. figure 17 shows an example of how to program the adv7196a to accept a different high definition standard but smpte293m, smpte274m, smpte296m or itu-r.bt1358 standard. input standard (mr04) select between 525p progressive scan input or 625p progressive scan input. reserved (mr05) a ??must be written to this bit. dv polarity (mr06) this control bit allows to select the polarity of the dv input control signal to be either active high or active low. this is in order to facilitate interfacing from i to p converters which use an active low blanking signal output. macrovision (mr07) to enable macrovision this bit must be set to ?. mr01 mr07 mr02 mr04 mr05 mr06 mr07 0 disabled 1 enabled macrovision mr03 mr00 zero must be written to this bit mr05 mr06 0 active high 1 active low dv polarity mr04 0 525p 1 625p input standard mr03 mr02 hsync \ vsync /dv eav/sav tsync/ synd /dv reserved input control signals mr01 mr00 0 0 eia-770.2 0 1 eia-770.1 1 0 full i/p range 1 1 reserved output standard selection 0 1 0 1 0 0 1 1 figure 16. mode register 0 rev. 0 adv7196a C15C table ii must be followed when programming the control sig- nals in async timing mode. table ii. truth table sync tsync dv 1 ? 0 0 0 or 1 50% point of falling edge of tri-level horizontal sync signal, a 0 0 ? 1 0 or 1 25% point of rising edge of tri-level horizontal sync signal, b 0 ? 1 0 or 1 0 50% point of falling edge of tri-level horizontal sync signal, c 1 0 or 1 0 ? 1 50% start of active video, d 1 0 or 1 1 ? 0 50% end of active video, e ab c d e clk sync tsync dv set mr06 = 1 programmable input timing analog output active video horizontal sync 66 81 66 243 1920 figure 17. async timing modeprogramming input control signals for smpte295m compatibility video output hsync 525 vsync dv 112134243 figure 18. dv input control signal in relation to video output signal rev. 0 adv7196a C16C vbi open (mr14) this bit enables or disables the facility of vbi data insertion during the vertical blanking interval. for this purpose lines 13 to 42 of each frame can be used for vbi when smpte293m standard is used, or lines 6 to 43 when itu-r.bt1358 standard is used . undershoot limiter (mr15?r16) this control limits the y signal to a programmable level in the active video region. available limit levels are ?.5 ire, ? ire, ?1 ire. note that this facility is only available when interpolation is enabled (mr36 = ?? . sharpness filter (mr17) this control bit enables or disables the sharpness filter mode. this bit must be set to ??for any values programmed into the filter gain 1 register to take effect. it must also be set to ??when adaptive filter mode is used. refer to sharpness filter control and adaptive filter control section. 6ire 100ire 0ire 40ire figure 19. undershoot limiter, programmed to C6 ire mode register 1 mr1 (mr17?r10) (address (sr4?r0) = 01h) figure 20 shows the various operations under the control of mode register 1. mr1 bit description pixel data enable (mr10) when this bit is set to ?,?the pixel data input to the adv7196a is blanked such that a black screen is output from the dacs. when this bit is set to ?,?pixel data is accepted at the input pins and the adv7196a outputs the standard set in ?utput standard selection?(mr01?0). this bit must be set to ??to enable out- put of the test pattern signals. input format (mr11) it is possible to input data in 4:2:2 format or at 4:4:4 format at 27 mhz. test pattern enable (mr12) enables or disables the internal test pattern generator. test pattern hatch/frame (mr13) if this bit is set to ?,?a cross-hatch test pattern is output from the adv7196a (for example, in smpte293m 11 horizontal and 11 vertical white lines, four pixels wide are displayed against a black background). the cross-hatch test pattern can be used to test monitor convergence. if this bit is set to ?,?a uniform colored frame/field test pattern is output from the adv7196a. the color of the lines or the frame/field is by default white but can be programmed to be any color using the color y, color cr, color cb registers. mr11 mr17 mr12 mr14 mr15 mr16 mr17 0 disabled 1 enabled sharpness filter mr13 mr10 mr14 0 disabled 1 enabled vbi open mr12 0 disabled 1 enabled test pattern enable mr10 0 disabled 1 enabled pixel data enable mr16 mr15 0 0 disabled 01 11ire 10 6ire 11 1.5ire undershoot limiter mr13 0hatch 1 field/frame test pattern hatch/frame mr11 0 4:4:4 ycrcb 1 4:2:2 ycrcb input format figure 20. mode register 1 rev. 0 adv7196a C17C mode register 2 mr1 (mr27?r20) (address (sr4?r0) = 02h) figure 22 shows the various operations under the control of mode register 2. mr2 bit description y delay (mr20?r22) this control bit delays the y signal with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. figure 21 demonstrates this facility . color delay (mr23?r25) this control allows delay of the color signals with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. figure 21 demonstrates this facility . cgms enable (mr26) when this bit is set to ?,?cgms data is inserted on line 41 in 525p mode. the cgms conforms: to cgms-a eia-j cpr1204-1, transfer method of video id information using vertical blanking interval (525p system), march 1998 and iec61880, 1998, video systems (525/60)?ideo and accompanied data using the vertical blanking interval?nalogue interface. the cgms data bits are programmed into the cgms data registers 0?. for more information refer to cgms data registers section . cgms crc (mr27) this bit enables the automatic cyclic redundancy check when cgms is enabled. max delay no delay no delay max delay prpb delay y delay y output prpb outputs figure 21. y and color delay mr21 mr27 mr22 mr24 mr25 mr23 mr20 mr26 mr27 0 disabled 1 enabled cgms crc mr26 0 disabled 1 enabled cgms enable mr25 mr24 mr23 0 0 0 0 pclk 0 0 1 1 pclk 0 1 0 2 pclk 0 1 1 3 pclk 1 0 0 4 pclk color delay mr22 mr21 mr20 0 0 0 0 pclk 0 0 1 1 pclk 0 1 0 2 pclk 0 1 1 3 pclk 1 0 0 4 pclk y delay figure 22. mode register 2 rev. 0 adv7196a C18C mode register 4 mr4 (mr47?r40) (address (sr4?r0) = 04h) figure 24 shows the various operations under the control of mode register 4. mr4 bit description timing reset (mr40) toggling mr40 from low to high and low again resets the inter- nal horizontal and vertical timing counters. mode register 5 mr5 (mr57?r50) (address (sr4?r0) = 05h) figure 25 shows the various operations under the control of mode register 5. mr5 bit description reserved (mr50) this bit is reserved for the revision code . rgb mode (mr51) when rgb mode is enabled (mr51 = ?? the adv7196a accepts unsigned binary rgb data at its input port. this control is also available in async timing mode . sync on prpb (mr52) by default the color component output signals pr, pb do not contain any horizontal sync pulses. they can be inserted when mr52 = ?.?this facility is only available when output stan dard selection has been set to eia-770.2 (mr01?0 = ?0? or full input range (mr01?0 = ?0?. this control is not available in rgb mode . mode register 3 mr3 (mr37?r30) (address (sr4?r0) = 03h) figure 23 shows the various operations under the control of mode register 3. mr3 bit description hdtv enable (mr30) when this bit is set to ??the adv7196a reverts to hdtv mode (refer to hdtv mode section). when set to ??the adv7196a is set up in progressive scan mode (ps mode) . reserved (mr31?r32) a ??must be written to these bits . dac a control (mr33) setting this bit to ??enables dac a, otherwise this dac is powered down . dac b control (mr34) setting this bit to ??enables dac b, otherwise this dac is powered down . dac c control (mr35) setting this bit to ??enables dac c, otherwise this dac is powered down . interpolation (mr36) this bit enables the second stage interpolation filters. when this bit is enabled (mr36 = ??. data is send at 54 mhz to the dac output stage. after reset it is recommended to toggle this bit. before toggling this bit 3ehex must be written to address 09hex to guarantee correct operations . reserved (mr37) a zero must be written to this bit . mr37 mr32 mr34 mr36 zero must be written to this bit mr37 mr34 0 power-down 1 normal dac b control mr35 mr36 0 disable 1 enable interpolation mr35 0 power-down 1 normal dac c control mr33 zero must be written to this bit mr32 mr31 mr30 0 disable 1 enable hdtv enable mr30 mr33 0 power-down 1 normal dac a control zero must be written to this bit mr31 figure 23. mode register 3 mr47 mr42 mr44 mr46 zero must be written to these registers mr47 mr41 mr45 mr43 mr41 mr40 mr40 timing reset figure 24. model register 4 rev. 0 adv7196a C19C color output swap (mr53) by default dac b is configured as the pr output and dac c as the pb output. in setting this bit to ??the dac outputs can be swapped around so that dac b outputs pb and dac c outputs pr. table iii demonstrates this in more detail. this control is also available in rgb mode . table iii. relationship between color input pixel port, mr53 and dac b, dac c outputs in 4:4:4 input mod e color data analog output input on pins mr53 signal cr9? 0 dac b cb/cr9? 0 dac c cr9? 1 dac c cb/cr9? 1 dac b in 4:2:2 input mod e color data analog output input on pins mr53 signal cr9? 0 or 1 not operational cb/cr9? 0 dac c (pb) cb/cr9? 1 dac c (pr) gamma curve (mr54) this bit selects which of the two programmable gamma curves is to be used. when setting mr54 to ?,?the gamma correction curve selected is curve a. otherwise curve b is selected. each curve will have to be programmed by the user as explained in the gamma correction registers section . gamma correction (mr55) to enable gamma correction and therefore activate the gamma curve programmed by the user, this bit must be set to ?.?otherwise the programmable gamma correction facility is bypassed. pro- gramming of the gamma correction curves is explained in the gamma correction registers section . adaptive mode control (mr56) for this control to be effective, adaptive filter control must be enabled (mr57 = ?? as well as the sharpness filter (mr17 = ??. for filter plots refer to sharpness filter control and adaptive filter control section . adaptive filter control (mr57) this bit enables the adaptive filter control when set to ?. sharpness filter must be enabled as well (mr17 = ??. the adaptive filter controls is explained in more detail under sharpness filter control and adaptive filter control section . color y cy (cy7?y0) (address (sr4?r0) = 06h cy7 cy6 cy5 cy4 cy3 cy2 cy1 cy0 cy7 cy0 color y value figure 26. color y register color cr ccr (ccr7?cr0) (address (sr4?r0) = 07h ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 ccr7 ccr0 color cr value figure 27. color cr register color cb ccb (ccb7?cb0) (address (sr4?r0) = 08h) ccb7 ccb6 ccb5 ccb4 ccb3 ccb2 ccb1 ccb0 ccb7 ccb0 color cb value figure 28. color cb register these three 8-bit-wide registers are used to program the output color of the internal test pattern generator, be it the lines of the cross-hatch pattern or the uniform field test pattern and are available in ps mode and hdtv mode. the standard used for the values for y and the color difference signals to obtain white, black and the saturated primary and complementary colors conforms to the itu-r bt 601-4 standard. color output swap reserved for revision code mr50 mr57 mr56 mr55 mr54 mr53 mr52 mr51 mr50 0 mode a 1 mode b mr56 adaptive mode control mr57 adaptive filter control 0 disable 1 enable mr55 gamma correction 0 disable 1 enable sync on prpb mr52 0 disable 1 enable 0 curve a 1 curve b mr54 gamma curve rgb mode mr51 0 disable 1 enable mr53 0 dac b = pr 1 dac c = pr figure 25. mode register 5 rev. 0 adv7196a C20C the table iv shows sample color values to be programmed into the color registers when output standard selection is set to eia-770.2 (mr01?0 = ?0? . table iv. sample color values for eia 770 . 2 output standard selectio n sample color y color cr color cb color value value value white 235 (eb) 128 (80) 128 (80) black 16 (10) 128 (80) 128 (80) red 81 (51) 240 (f0) 90 (5a) green 145 (91) 34 (22) 54 (36) blue 41 (29) 110 (6e) 240 (f0) yellow 210 (d2) 146 (92) 16 (10) cyan 170 (aa) 16 (10) 166 (a6) magenta 106 (6a) 222 (de) 202 (ca) mode register 6 mr6 (mr67?r60) (address (sr4?r0) = 09h) figure 29 shows the various operations under the control of mode register 6 . mr6 bit description mr67?r60 the value 3ehex must be written to this register before the pll is reset (reset mr36) to guarantee correct operation of the adv7196a. mr67 zero must be written to this bit mr60 mr66 mr65 mr64 mr63 mr62 mr61 mr60 one must be written to this bit mr62 one must be written to this bit mr64 zero must be written to this bit mr66 one must be written to this bit mr61 one must be written to this bit mr63 one must be written to this bit mr65 zero must be written to this bit mr67 figure 29. mode register 6 cgms data registers 2 0 cgms2 (cgms27?gms20) (address (sr4?r0) = 13h) this 8-bit-wide register contains the last four cgms data bits, (c16?19) of the cgms data stream. cgms23 cgms20 cgms2 cgms27 cgms26 cgms25 cgms24 cgms23 cgms22 cgms21 cgms20 cgms27 cgms24 zero must be written to these bits figure 30. cgms2 data register cgms1 (cgms17?gms10) (address (sr4?r0) = 12h) this 8-bit-wide register contains (c8?15) of the cgms data stream. cgms17 cgms10 cgms1 cgms17 cgms16 cgms15 cgms14 cgms13 cgms12 cgms11 cgms10 figure 31. cgms1 data register cgms0 (cgms07?gms00) (address (sr4?r0) = 11h) this 8-bit-wide register contains the first eight cgms data bits, (c0?7) of the cgms data stream. cgms07 cgms00 cgms0 cgms07 cgms06 cgms05 cgms04 cgms03 cgms02 cgms01 cgms00 figure 32. cgms0 data register crc sequence 21.2 s 0.22 s 22t ref c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 700mv (70 10)% 0mv 300mv bit1 bit2...................................................................................................................... ..........................bit20 5.8 s 0.15 s 6t t = 1/(fh 33) = 963ns fh = horizontal scan frequency t 30ns figure 33. cgms waveform rev. 0 adv7196a C21C the response of the curve is programmed at seven predefined locations. in changing the values at these locations the gamma curve can be modified. between these points linear interpolation is used to generate intermediate values. considering the curve to have a total length of 256 points, the seven locations are at: 32, 64, 96, 128, 160, 192, 224. location 0, 16, 240, and 255 are fixed and can not be changed. for the length of 16 to 240 the gamma correction curve has to be calculated as below: y = x where: y = gamma corrected output . x = linear input signal . = gamma power factor. to program the gamma correction registers, the seven values for y have to be calculated using the following formula: y n = [ x (n?6) /(240 ?16)] (240) ?16) + 16 where: x (n?6) = value for x along x-axis at points: n = 32, 64, 96, 128, 160, 192, or 224 . y n = value for y along the y-axis, which has to be written into the gamma correction register. example: y 32 = [(16/22 4)0 . 5 2 24] + 16 = 76 * y 64 = [(48/22 4)0 . 5 224] + 16 =120 * y 96 = [(80/22 4)0 . 5 224] + 16 = 150 * y 128 = [(112/22 4)0 . 5 224] + 16 = 147 * * rounded to the nearest integer. the above will result in a gamma curve shown below, assuming a ramp signal as an input. 250 200 150 100 50 0 300 signal output signal input 0.5 gamma correction block output to a ramp input gamma-corrected amplitude 0 50 100 150 200 250 location figure 35. signal input (ramp) and signal output for gamma 0.5 filter gain fg (fg7?g0) (address (sr4?r0) = 10h) figure 34 shows the various operations under the control of the filter gain register . fg7 fg6 fg5 fg4 fg3 fg2 fg1 fg0 fg7 fg4 filter gain b 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 7 1010 6 1011 5 1100 4 1101 3 1110 2 1111 1 fg3 fg0 filter gain a 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 7 1010 6 1011 5 1100 4 1101 3 1110 2 1111 1 figure 34. filter gain register fg bit description filter gain a (fg3?g0) these bits are used to program the gain a value, which varies from response ? to response +7 and are applied to filter a. filter gain b (fg4?g7) these bits are used to program the gain b value, which varies from response ? to response +7 and are applied to filter b. refer to sharpness filter control and adaptive filter control section for more detail. gamma correction registers 0?3 (gamma correction 0?3) (address (sr5?r0) = 14h?1h) the gamma correction registers are fourteen 8-bit-wide register. they are used to program the gamma correction curves a and b. generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the crt). it can also be applied whe rever nonlinear processing is used. gamma correction uses the function: signal out = (signal in ) where = gamma power factor. gamma correction is performed on the luma data only. the user has the choice to use two different curves, curve a or curve b. at any one time only one of these curves can be used. rev. 0 adv7196a C22C 250 200 150 100 50 0 300 signal outputs signal input 0.5 gamma correction block output to a ramp input for various gamma values gamma-corrected amplitude 0 50 100 150 200 250 location 0.3 1.5 1.8 figure 36. signal input (ramp) and selectable gamma output curves the gamma curves shown above are examples only, any user defined curve is acceptable in the range of 16?40 . sharpness filter control and adaptive filter control there are three filter modes available on the adv7196a: one sharpness filter mode and two adaptive filter modes. sharpness filter mode to enhance or attenuate the y signal in the frequency ranges shown in figure 37, the following register settings must be used: sharpness filter must be enabled (mr17 = ?? and adaptive filter control must be disabled (mr57 = ??. to select one of the 256 individual responses, the according gain values for each filter, which range from ? to +7, must be pro- grammed into the filter gain register . adaptive filter mode the adaptive filter threshold a, b, c registers, the adaptive filter gain 1, 2, 3 registers and the filter gain register are used in adaptive filter mode. to activate the adaptive filter control, sharpness filter must be enabled (mr17 = ?? and adaptive filter control must be enabled (mr57 = ??. the derivative of the incoming signal is compared to the three pro- grammable threshold values: adaptive filter threshold a, b, c. the edges can then be attenuated with the settings in adaptive filter gain 1, 2, 3 registers and filter gain register. according to the settings of the adaptive mode control (mr56), there are two adaptive filter modes available: 1. mode a: is used when adaptive filter mode (mr56) is set to ?.?in this case, filter b (lpf) will be used in the ada ptive filter block. also, only the programmed values for gain b in the filter gain, adaptive filter gain 1, 2, 3 are applied when needed. the gain a values are fixed and can not be changed. 2. mode b: is used when adaptive filter mode (mr56) is set to ?.?in this mode a cascade of filter a and filter b is used. both settings for gain a and gain b in the filter gain, adaptive filter gain 1, 2, 3 become active when needed . frequency mhz magnitude 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 02468101214 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 frequency mhz magnitude 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 02468101214 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 sharpness and adaptive filter control mode input signal: step frequency mhz magnitude response linear scale 1.6 1.5 1.4 1.3 1.2 1.1 1.0 02468101214 frequency response in sharpness filter mode with k a = 3 and k b = 7 figure 37. sharpness and adaptive filter control mode rev. 0 adv7196a C23C adaptive filter gain 1 afg1 (afg1)7? (address (sr5?r0) = 22h) this 8-bit-wide register is used to program the gain applied to signals which lie above adaptive filter threshold a but are smaller than adaptive filter threshold b. gain a and gain b values vary from ? to +7. the individual responses are shown in the figures below. settings for (afg1)3? have no effect unless adaptive mode con- trol is set to mode b (mr56 = ??. afg13 afg10 gain a afg17 afg16 afg15 afg14 afg13 afg12 afg11 afg10 afg17 afg14 gain b figure 38. adaptive filter gain 1 register adaptive filter gain 2 afg2 (afg2)7? (address (sr5?r0) = 23h) this 8-bit-wide register is used to program the gain applied to signals which lie above adaptive filter threshold b but are smaller than adaptive filter threshold c. gain a and gain b values vary from ? to +7. the individual responses are shown in the figures below. settings for (afg2)3? have no effect unless adaptive mode con- trol is set to mode b (mr56 = ??. afg23 afg20 gain a afg27 afg26 afg25 afg24 afg23 afg22 afg21 afg20 afg27 afg24 gain b figure 39. adaptive filter gain 2 register adaptive filter gain 3 afg3 (afg3)7? (address (sr5?r0) = 24h) this 8-bit-wide register is used to program the gain applied to signals which lie above adaptive filter threshold c gain a and gain b values vary from ? to +7. the individual responses are shown in the figures below. settings for (afg3)3? have no effect unless adaptive mode con- trol is set to mode b (mr56 = ??. the gain applied to signals which lie below adaptive threshold a are programmed in the filter gain register. at any one time only one of the following registers is active: afg1, afg2, afg3, fg. the gain values can be preprogrammed and become active whenever the threshold conditions for the accord- ing register is met. to program the adaptive filter gain registers the source register settings are used as for the filter gain register . afg33 afg30 gain a afg37 afg36 afg35 afg34 afg33 afg32 afg31 afg30 afg37 afg34 gain b figure 40. adaptive filter gain 3 register adaptive filter threshold a afta (afta)7? (address (sr5?r0) = 25h) this 8-bit-wide register is used to program the threshold value for small edges. the recommended programmable threshold range is from 16?35, although any value in the range of 0?55 can be used. afta7 afta0 adaptive filter threshold a afta7 afta6 afta5 afta4 afta3 afta2 afta1 afta0 figure 41. adaptive filter threshold a register adaptive filter threshold b aftb (aftb)7? (address (sr5?r0) = 26h) this 8-bit-wide register is used to program the threshold value for medium edges and has priority over adaptive threshold a. the recommended programmable threshold range is from 16?35, although any value in the range of 0?55 can be used. aftb7 aftb0 adaptive filter threshold b aftb7 aftb6 aftb5 aftb4 aftb3 aftb2 aftb1 aftb0 figure 42. adaptive filter threshold b register adaptive filter threshold c aftc (aftc)7? (address (sr5?r0) = 27h) this 8-bit-wide register is used to program the threshold value for large edges and has priority over adaptive threshold a and b. the recommended programmable threshold range is from 16 ?35, although any value in the range of 0?55 can be used. aftc7 aftc0 adaptive filter threshold c aftc7 aftc6 aftc5 aftc4 aftc3 aftc2 aftc1 aftc0 figure 43. adaptive filter threshold c register rev. 0 adv7196a C24C sharpness filter and adaptive filter application examples sharpness filter application the sharpness filter can be used to enhance or attenuate the y video output signal. the following register settings were used to achieve the results shown in the figures below: input data was generated by an external signal source . table v. address register setting 00hex mode register 0 40hex 01hex mode register 1 81hex 02hex mode register 2 00hex 03hex mode register 3 78hex 04hex mode register 4 00hex 05hex mode register 5 00hex 09hex mode register 6 3ehex 10hex filter gain 00hex (a) 10hex filter gain 08hex (b) 10hex filter gain 04hex (c) 10hex filter gain 40hex (d) 10hex filter gain 80hex (e) 10hex filter gain 22hex (f) ch1 t r2 r4 1 (b) (c) (a) tek run t trig d 500mv m 4.00 s ref4 500mv 4.00 s 9.99976ms t ch1 all fields (a) ch1 t r2 r1 1 (e) (f) (d) tek run t trig d 500mv m 4.00 s ref2 500mv 4.00 s 9.99976ms t ch1 all fields (b) figure 44. sharpness filter control with different gain settings for filter gain the effect of the sharpness filter can also be seen when using the internally generated cross hatch pattern : table vi. address register setting 00hex mode register 0 00hex 01hex mode register 1 85hex 02hex mode register 2 00hex 03hex mode register 3 38hex 04hex mode register 4 00hex 05hex mode register 5 00hex 09hex mode register 6 3ehex rev. 0 adv7196a C25C in toggling mr17 (sharpness filter enable/disable) and setting the filter gain register value to 99hex it can be seen that the line contours of the cross hatch pattern change their sharpness . adaptive filter control application the figure below shows a typical signal to be processed by the adaptive filter control block. t 4 tek run t trig d m 100ns 12.8222ms t ch4 all fields ch4 100mv figure 45. input signal to adaptive filter control the following register settings where used to obtain the results s hown in the figure below, i.e., to remove the ringing on the y signal: input data was generated by an external signal source. table vii. address register setting 00hex mode register 0 40hex 01hex mode register 1 81hex 02hex mode register 2 00hex 03hex mode register 3 78hex 04hex mode register 4 00hex 05hex mode register 5 80hex 09hex mode register 6 3ehex 10hex filter gain 00hex 22hex adaptive filter gain 1 achex 23hex adaptive filter gain 2 9ahex 24hex adaptive filter gain 3 88hex 25hex adaptive filter threshold a 28hex 26hex adaptive filter threshold b 3fhex 27hex adaptive filter threshold c 64hex the figure below shows the output signal when changing the a dap- tive filter mode to mode b (mr56 = ??. t 4 tek run t trig d m 100ns 12.8222ms t ch4 all fields ch4 100mv figure 46. output signal from adaptive filter control the adaptive filter control can also be demonstrated using the internally generated crosshatch test pattern and toggling the adap- tive filter control bit (mr57) using the following register settings: table viii. address register setting 00hex mode register 0 40hex 01hex mode register 1 85hex 02hex mode register 2 00hex 03hex mode register 3 78hex 04hex mode register 4 00hex 05hex mode register 5 80hex 06hex color y 6chex 07hex color cr 52hex 08hex color cb 52hex 09hex mode register 6 3ehex 10hex filter gain 00hex 22hex adaptive filter gain 1 achex 23hex adaptive filter gain 2 9ahex 24hex adaptive filter gain 3 88hex 25hex adaptive filter threshold a 28hex 26hex adaptive filter threshold b 3fhex 27hex adaptive filter threshold c 64hex t 4 t ek run t trig d m 100ns 12.8222ms t ch4 all fields ch4 100mv figure 47. output signal from adaptive filter control rev. 0 adv7196a C26C hdtv mode mode register 0 mr0 (mr07?r00) (address (sr4?r0) = 00h) figure 50 shows the various operations under the control of mode register 0. hexmr0 bit description output standard selection (mr00?r01) these bits are used to select the output levels from the adv7196a. if eia 770.3 (mr01?0 = ?0? is selected, the output levels will be: 0 mv for blanking level, 700 mv for peak white (y channel), 350 mv for pr, pb outputs and ?00 mv for tri-level sync. if full input range (mr01?0 = ?0? is selected, the output levels will be 700 mv for peak white for the y channel, 350 mv for pr, pb outputs and ?00 mv for sync. this mode is used for rs-170, rs-343a standard output compatibility. sync insertion on the pr, pb channels is optional. for output levels, refer to the appendix . input control signals (mr02?r03) these control bits are used to select whether data is input with external horizontal, vertical and blanking sync signals or if the data is input with embedded eav/sav code an asynchronous timing mode is also available using tsync, sync and dv as input control signals. these timing control signals have to be pr ogrammed by the user. figure 48 shows an example of how to program the adv7196a to accept a different high definition standard but smpte293m, smpte274m, smpte296m or itu-r.bt1358 standard . reserved (mr04) a ??must be written to this bit . input standard (mr05) select between 1080i or 720p input . dv polarity (mr06) this control bit allows to select the polarity of the dv input control signal to be either active high or active low . reserved (mr07) a ??must be written to this bit . table ix. truth table sync tsync dv 1 ? 0 0 0 or 1 50% point of falling edge of tri-level horizontal signal, a 0 0 ? 1 0 or 1 25% point of rising edge of tri-level horizontal signal, b 0 ? 1 0 or 1 0 50% point of falling edge of tri-level horizontal signal, c 1 0 or 1 0 ? 1 50% start of active video, d 1 0 or 1 1 ? 0 50% end of active video, e clk sync tsync dv set mr06 = 1 programmable input timing analog output ab c d e 243 active video 1920 66 66 81 horizontal sync figure 48. async timing modeprogramming input control signals for smpte295m compatibility 7 video output hsync 525 vsync dv 1 12 13 42 43 figure 49. dv input control signal in relation to video output signal rev. 0 adv7196a C27C mode register 1 mr1 (mr17?r10) (address (sr4-sr0) = 01h) figure 51 shows the various operations under the control of mode register 1. mr1 bit description pixel data enable (mr10) when this bit is set to ?,?the pixel data input to the adv7196a is blanked such that a black screen is output from the dacs. when this bit is set to ?,?pixel data is accepted at the input pins and the adv7196a outputs to the standard set in ?utput standard selection?(mr01?0). this bit also must be set to ??to enable output pattern signals . input format (mr11) it is possible to input data in 4:2:2 format or in 4:4:4 hdtv format . test pattern enable (mr12) enables or disables the internal test pattern generator . test pattern hatch/frame (mr13) if this bit is set to ?,?a cross-hatch test pattern is output from the adv7196a. the cross-hatch test pattern can be used to test monitor convergence. if this bit is set to ?,?a uniform colored frame/field test pattern is output from the adv7196a. the color of the lines or the frame/field is by default white but can be programmed to be any color using the color y, color cr, color cb registers . vbi open (mr14) this bit enables or disables the facility of vbi data insertion during the vertical blanking interval. for this purpose lines 7?0 in 1080i and lines 6?5 in 720p can be used for vbi data insertion . reserved (mr15?r17) a ??must be written to these bits . mr01 mr07 mr02 mr04 mr06 mr07 zero must be written to this bit mr03 mr00 mr03 mr02 00 hsync / vsync /dv 0 1 eav/sav 1 0 tsync/ sync /dv 1 1 reserved input control signals mr05 mr06 0 active high 1 active low dv polarity mr05 0 1080i 1 720p input standard mr04 zero must be written to this bit mr01 mr00 0 0 eia770.3 0 1 reserved 1 0 full i/p range 1 1 reserved output standards selection figure 50. mode register 0 mr11 mr17 mr12 mr14 mr16 mr13 mr10 mr14 0 disabled 1 enabled vbi open mr12 0 disabled 1 enabled test pattern enable mr10 0 disabled 1 enabled pixel data enable mr13 0hatch 1 field/frame test pattern hatch/frame mr11 0 4:4:4 ycrcb 1 4:2:2 ycrcb input format mr15 mr17 mr15 zero must be written to these bits figure 51. mode register 1 rev. 0 adv7196a C28C mode register 2 mr1 (mr27?r20) (address (sr4?r0) = 02h) figure 53 shows the various operations under the control of mode register 2. mr2 bit description y delay (mr20?r22) with these bits it is possible to delay the y signal with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. figure 52 demonstrates this facility. color delay (mr23?r25) with theses bits it is possible to delay the color signals with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. figure 52 demonstrates this facility. reserved (mr26?r27) a ??must be written to these bits . max delay no delay no delay max delay prpb delay y delay y output prpb outputs figure 52. y and color delay mode register 3 mr3 (mr37?r30) (address (sr4-sr0) = 03h) figure 54 shows the various operations under the control of mode register 3 . mr3 bit description hdtv enable (mr30) when this bit is set to ??the adv7196a reverts to hdtv mode. when set to ??the adv7196a reverts to progressive scan mode (ps mode). reserved (mr31?r32) a ??must be written to these bits. dac a control (mr33) setting this bit to ??enables dac a, otherwise this dac is powered down. dac b control (mr34) setting this bit to ??enables dac b, otherwise this dac is powered down. dac c control (mr35) setting this bit to ??enables dac c, otherwise this dac is powered down. reserved (mr36?r37) a ??must be written to these bits. mr21 mr27 mr22 mr24 mr25 mr23 mr20 mr26 mr25 mr24 mr23 0 0 0 0 pclk 0 0 1 1 pclk 0 1 0 2 pclk 0 1 1 3 pclk 1 0 0 4 pclk color delay mr22 mr21 mr20 0 0 0 0 pclk 0 0 1 1 pclk 0 1 0 2 pclk 0 1 1 3 pclk 1 0 0 4 pclk y delay mr27 mr26 zero must be written to these bits figure 53. mode register 2 mr37 mr32 mr34 mr36 zero must be written to these bits mr37 mr36 mr34 0 power-down 1 normal dac b control mr35 mr35 0 power-down 1 normal dac c control mr33 zero must be written to these bits mr32 mr31 mr31 mr30 0 disable 1 enable hdtv enable mr30 mr33 0 power-down 1 normal dac a control figure 54. mode register 3 rev. 0 adv7196a C29C mode register 4 mr4 (mr47?r40) (address (sr4?r0) = 04h) figure 55 shows the various operations under the control of mode register 4. mr4 bit description timing reset (mr40) toggling mr40 from low to high and low again resets the inter- nal horizontal and vertical timing counters . mode register 5 mr5 (mr57?r50) (address (sr4?r0) = 05h) figure 56 shows the various operations under the control of mode register 5. mr5 bit description reserved (mr50) these bit is reserved for the revision code . rgb mode (mr51) when rgb mode is enabled (mr51 = ?? the adv7196a accepts unsigned binary rgb data at its input port. this control is also available in async timing mode . sync on prpb (mr52) by default the color component output signals pr, pb do not contain any horizontal sync pulses. if required they can be inserted when mr52 = ?.?this control is not available in rgb mode . color output swap (mr53) by default dac b is configured as the pr output and dac c as the pb output. in setting this bit to ??the dac outputs can be swapped around so that dac b outputs pb and dac c outputs pr. table x demonstrates this in more detail. reserved (mr54?r57) ??must be written to these bits. table x. relationship between input pixel port, mr53 and dac b, dac c outputs in 4:4:4 input mod e color data analog output input on pins mr53 signal cr9? 0 dac b cb/cr9? 0 dac c cr9? 1 dac c cb/cr9? 1 dac b in 4:2:2 input mod e color data analog output input on pins mr53 signal cr9? 0 or 1 not operational cb/cr9? 0 dac c (pb) cb/cr9? 1 dac c (pr) mr47 mr42 mr44 mr46 zero must be written to these bits mr47 mr41 mr45 mr43 mr41 mr40 mr40 timing reset figure 55. mode register 4 mr57 mr52 mr56 mr57 mr54 zero must be written to these bits mr55 mr53 mr51 mr50 mr54 mr53 0 dac b = pr 1 dac c = pr color output swap mr52 0 disable 1 enable sync on prpb mr51 0 disable 1 enable rgb mode reserved for revision code mr50 figure 56. mode register 5 rev. 0 adv7196a C30C dac termination and layout considerations voltage reference the adv7196a contains an on-board voltage reference. the v ref pin is normally terminated to v aa through a 0.1 f capacitor when the internal v ref is used. alternatively, the adv7196a can be used with an external v ref (ad589). resistor r set is connected between the r set pin and agnd and is used to control the full-scale output current and therefore the dac voltage output levels. for full-scale output r set must have a value of 2470 ? . r load has a value of 300 ? . when an input range of 0?023 is selected the value of r set must be 2820 ? . the adv7196a has three analog outputs, corresponding to y, pr, pb video signals. the dacs must be used with external buffer circuits in order to provide sufficient current to drive an output device. suitable op amps are the ad8009, ad8002, ad8001, or ad 8057. to calculate the output full-scale current and voltage the follow- ing equations should be used: v out = i out r load i out = [ v ref k ] /r se t where: k = 5.66 [for input ranges 64?40, 64?60, output standards eia770.1?] k = 6.46 [for input ranges 0?023, output standard rs?7 0/343a] v ref = 1.235 v pc board layout considerations the adv7196a is optimally designed for lowest noise performance, both radiated and conducted noise. to complement the excellent noise performance of the adv7196a, it is imperative that great care be given to the pc board layout. the layout should be optimized for lowest noise on the adv7196a power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and agnd and v dd and dgnd pins should be kept as short as possible to minimized inductive ringing. it is recommended that a four-layer printed circuit board is used. with power and ground planes separating the layer of the signal carrying traces of the components and solder side lay er. placement of components should consider to separate noisy circuits, such as crystal clocks, high-speed logic circuitry and analog circuitry. there should be a separate analog ground plane (agnd) and a separate digital ground plane (gnd). power planes should encompass a digital power plane (v dd ) and a analog power plane (v aa ). the analog power plane should contain the dacs and all associated circuitry, and the v ref circuitry. the digital power plane should contain all logic circuitry. the analog and digital power planes should be individually connected to the common power plane at one single point through a suitable filter- ing device, such as a ferrite bead. 300 5k 5k mpu bus 4.7k v dd power supply decoupling for each power supply group alsb dv reset clkin r set sda scl dac a v dd vsync /tsync adv7196a unused inputs should be grounded dac b 100 hsync / sync dac c 27mhz, 74.25mhz or 74.1758mhz clock 4.7k 4.7 f 6.3v 300 300 100 2.47k or 2.82k 10nf 0.1 f y output pr (v) output pb (u) output v ref gnd 13, 52 agnd 26, 33 y0 y9 cr0 cr9 cb/cr0 cb/cr9 0.1 f 10nf 0.1 f 24, 35 1, 12 v dd v aa comp v aa v aa v dd v dd v dd figure 57. circuit layout rev. 0 adv7196a C31C adv7196a dac a dac b dac c ad8057 +5v +5v 75 coax 75 ad8057 5v 0.1 f10 f +5v 75 coax 75 ad8057 5v +5v 75 coax 75 progressive scan monitor 75 lpf lpf lpf 0.1 f10 f 0.1 f10 f 0.1 f10 f 0.1 f10 f 0.1 f10 f 75 75 figure 58. output buffer and optional filter dac output traces on a pcb should be treated as transmission lines. it is recommended that the dacs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches). the dac termina- tion re sistors should be placed as close as possible to the dac outputs and should overlay the pcb? ground plane. as well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry . supply decoupling noise on the analog power plane can be further reduced by the use of decoupling capacitors. optimum performance is achieved by the use of 0.1 f ceramic capacitors. each of group of v aa or v dd pins should be indi- vidually decoupled to ground. this should be done by placing the capacitors as close as possible to the device with the capaci- tor leads as short as possible, thus minimizing lead inductance . digital signal interconnect the digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, long clock lines to the adv7196a should be avoided to minimize noise pickup. any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane . analog signal interconnect the adv7196a should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch. for optimum performance, the analog outputs should each have a source termination resistance to ground of 75 ? . this termina- tion resistance should be as close as possible to the adv7196a to minimize reflections. any unused inputs should be tied to ground . video output buffer and optional output filter output buffering is necessary in order to drive output devices , such as progressive scan or hdtv monitors . analog devices produces a range of suitable op amps for this application. suitable op amps would be the ad8009, ad8002, ad8001, or ad8057. more information on line driver buffering circuits is given in the relevant op amp data sheets. rev. 0 adv7196a C32C register settings table xi. register settings on power-u p address register setting 00hex mode register 0 00hex 01hex mode register 1 00hex 02hex mode register 2 00hex 03hex mode register 3 38hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex color y a0hex 07hex color cr 80hex 08hex color cb 80hex 09hex mode register 6 00hex 10hex filter gain 00hex 22hex adaptive filter gain 1 achex 23hex adaptive filter gain 2 9ahex 24hex adaptive filter gain 3 88hex 25hex adaptive filter threshold a 28hex 26hex adaptive filter threshold b 3fhex 27hex adaptive filter threshold c 64he x table xii. i nternal colorbars (hatch), progressive scan mod e address register setting 00hex mode register 0 00hex 01hex mode register 1 05hex 02hex mode register 2 00hex 03hex mode register 3 38hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex color y xxhex 07hex color cr xxhex 08hex color cb xxhex 09hex mode register 6 3ehe x table xiii. internal colorbars (field), hdtv scan mod e address register setting 00hex mode register 0 00hex 01hex mode register 1 0dhex 02hex mode register 2 00hex 03hex mode register 3 39hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex color y xxhex 07hex color cr xxhex 08hex color cb xxhex an optional analog reconstruction lpf might be required as an antialias filter if the adv7196a is connected to a device that requires this filtering. the eval adv7196a/7eb evaluation board uses the ml6426 microlinear ic, which provides buffering and low-pass filtering for progressive scan applications. the eval adv7196a/7eb rev b and rev c evaluation board uses the ad8057 as a buffer and a 6th order lpf. ad8057 600r 18pf 2.2 h 22pf 10 h 6.8pf 6.8 h 600r figure 59. example for output filter: ps mode/ 2x oversampling 0 1m 5 10 15 20 25 30 35 23456789 10m frequency hz 234 498 63n 398 54n 298 45n 198 36n 97.6 27n 0 18n 102 9n 202 0n magnitude (db) phase (deg) group delay (sec) figure 60. frequency response for filter current in above figure rev. 0 adv7196a C33C 940 64 active video 700mv 0mv 300mv output voltage input code eia-770.2, standard for y 960 64 active video 350mv 300mv 350mv output voltage eia-770.2, standard forpr/pb 0mv 512 figure 61. eia -770.2 standard output signals (525p) 940 64 714mv 0mv 286mv output voltage input code eia-770.1, standard for y active video 782mv 960 64 active video 350mv 300mv 350mv output voltage eia-770.1, standard forpr/pb 0mv 512 figure 62. eia -770.1 standard output signals (525p) 940 64 active video 700mv 300mv 300mv output voltage input code eia-770.3, standard for y 0mv 960 64 active video 350mv 300mv 300mv output voltage eia-770.3, standard for pr/pb 0mv 512 350mv figure 63. eia -770.3 standard output signals (1080i, 720p) 1023 64 active video 700mv 0mv 300mv output voltage input code y-output levels for full i/p sections 1023 64 active video 700mv 300mv output voltage prpb-output levels for full i/p sections 0mv input code figure 64. output levels for full i/p selection rev. 0 adv7196a C34C f f 0 0 input pixels 0 0 f v h * f f 0 0 f v h * 0 0 c b y c r y c r y 4 clock 853 799 857 0 719 736 723 719 4 clock digital horizontal blanking sample number ancillary data (optional) sav code eav code digital active line analog waveform smpte293m 0hdatum fvh * = fvh and parity bits sav: line 43 525 = 200h sav: line 1 42 = 2ac eav: line 43 525 = 274h eav: line 1 42 = 2d8 figure 65. eav/sav input data timing diagramsmpte293m f f 0 0 input pixels 0 0 f v h * f f 0 0 f v h * 0 0 c b y c r c r y 4 clock sample number eav code digital active line analog waveform smpte274m 4 clock 2112 2116 2156 2199 440 188 192 2111 4t sav code 4t 1920t 272t ancillary data (optional) or blanking code digital horizontal blanking 0hdatum fvh * = fvh and parity bits sav/eav: line 1 562: f = 0 sav/eav: line 563 1125: f = 1 sav/eav: line 1 20; 561 583; 1124 1125: v = 1 sav/eav: line 21 560; 584 1123: v = 0 0 figure 66. eav/sav input data timing diagramsmpte274m rev. 0 adv7196a C35C 522 523 524 525 1 2 5 6 7 8 9 12 13 10 11 active video 12 42 43 44 active video vertical blank figure 67. smpte293m (525p) 622 623 624 625 1 2 4 5 6 7 8 9 10 11 12 active video 13 43 44 45 active video vertical blank figure 68. itu-r. bt1358 (625p) 747 748 749 750 1 2 3 4 5 6 7 8 25 26 27 744 745 display vertical blanking interval figure 69. smpte296m (720p) 1124 1125 1 2 3 4 5 6 7 8 20 21 22 560 display vertical blanking interval field 1 561 562 563 564 565 566 567 568 569 570 583 584 585 1123 display vertical blanking interval field 2 figure 70. smpt274m (1080i) rev. 0 adv7196a C36C 52-lead plastic quad flatpack (mqfp) (s-52) top view (pins down) 1 13 14 27 26 39 40 52 pin 1 0.014 (0.35) 0.010 (0.25) 0.557 (14.15) 0.537 (13.65) 0.398 (10.11) 0.390 (9.91) 0.557 (14.15) 0.537 (13.65) 0.398 (10.11) 0.390 (9.91) 0.0256 (0.65) bsc 0.082 (2.09) 0.078 (1.97) 0.012 (0.30) 0.006 (0.15) 0.008 (0.20) 0.006 (0.15) seating plane 0.037 (0.95) 0.026 (0.65) 0.094 (2.39) 0.084 (2.13) outline dimensions dimensions shown in inches and (mm). c02154C1.5C4/01(0) printed in u.s.a. |
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